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pre-production this is a product in the pre-production phase of development. device ramtron international corporation characterization is complete and ramtron does not expect to change the 1850 ramtron drive, colorado springs, co 80921 specifications. ramtron will issue a product change notice if any (800) 545-fram, (719) 481-7000 specification changes are made. http://www.ramtron.com rev. 2.0 may 2010 page 1 of 16 fm25v10 1mb serial 3v f-ram memory features 1m bit ferroelectric nonvolatile ram ? organized as 131,072 x 8 bits ? high endurance 100 trillion (10 14 ) read/writes ? 10 year data retention ? nodelay? writes ? advanced high-reliability ferroelectric process very fast serial peripheral interface - spi ? up to 40 mhz frequency ? direct hardware replacement for serial flash ? spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) write protection scheme ? hardware protection ? software protection device id and serial number ? device id reads out manufacturer id & part id ? unique serial number (fm25vn10) low voltage, low power ? low voltage operation 2.0v ? 3.6v ? 90 a standby current (typ.) ? 5 a sleep mode current (typ.) industry standard configurations ? industrial temperature -40 c to +85 c ? 8-pin ?green?/rohs soic package description the fm25v10 is a 1-megabit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile and performs reads and writes like a ram. it provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by serial flash and other nonvolatile memories. unlike serial flash, the fm25v10 performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after it has been transferred to the device. the next bus cycle may commence without the need for data polling. the product offers very high write endurance, orders of magnitude more endurance than serial flash. also, f-ram exhibits lower power consumption than serial flash. these capabilities make the fm25v10 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of serial flash can cause data loss. the fm25v10 provides substantial benefits to users of serial flash as a hardware drop-in replacement. the devices use the high-speed spi bus, which enhances the high-speed write capability of f-ram technology. the fm25vn10 is offered with a unique serial number that is read-only and can be used to identify a board or system. both devices incorporate a read-only device id that allows the host to determine the manufacturer, product density, and product revision. the devices are guaranteed over an industrial temperature range of -40c to +85c. pin configuration s q w vss vdd hold c d 1 2 3 4 8 7 6 5 pin name function /s chip select /w write protect /hold hold c serial clock d serial data input q serial data output vdd supply voltage vss ground
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 2 of 16 instruction decode clock generator control logic write protect instruction register address register counter 16384 x 64 fram array 17 data i/o register 8 nonvolatile status register 3 w s c q d hold figure 1. block diagram pin descriptions pin name i/o description /s input chip select: this active-low input activates the device. when high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. when low, the device internally activates the c signal. a falling edge on /s must occur prior to every op-code. c input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 40 mhz and may be interrupted at any time. /hold input hold: the /hold pin is used when the host cpu must interrupt a memory operation for another task. when /hold is low, the current operation is suspended. the device ignores any transition on c or /s. all transitions on /hold must occur while c is low. this pin has a weak internal pull-up (see r in spec, pg 11). however, if it is not used, the /hold pin should be tied to v dd . /w input write protect: this active-low pin prevents write operations to the status register only. a complete explanation of write protection is provided on pages 6 and 7. if it is not used, the /w pin should be tied to v dd . d input serial input: all data is input to the device on this pin. the pin is sampled on the rising edge of c and is ignored at other times. it should always be driven to a valid logic level to meet i dd specifications. * d may be connected to q for a single pin data interface. q output serial output: this is the data output pin. it is driven during a read and remains tri- stated at all other times including when /hold is low. data transitions are driven on the falling edge of the serial clock. * q may be connected to d for a single pin data interface. vdd supply power supply vss supply ground
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 3 of 16 overview the fm25v10 is a serial f-ram memory. the memory array is logically organized as 131,072 x 8 and is accessed using an industry standard serial peripheral interface or spi bus. functional operation of the f-ram is similar to serial flash. the major differences between the fm25v10 and a serial flash with the same pinout are the f-ram?s superior write performance, very high endurance, and lower power consumption. memory architecture when accessing the fm25v10, the user addresses 128k locations of 8 data bits each. these data bits are shifted serially. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a three- byte address. the complete address of 17-bits specifies each byte address uniquely. most functions of the fm25v10 either are controlled by the spi interface or are handled automatically by on-board circuitry. the access time for memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike serial flash, it is not necessary to poll the device for a ready condition since writes occur at bus speed. so, by the time a new bus transaction can be shifted into the device, a write operation will be complete. this is explained in more detail in the interface section. users expect several obvious system benefits from the fm25v10 due to its fast write cycle and high endurance as compared to serial flash. in addition there are less obvious benefits as well. for example in a high noise environment, the fast-write operation is less susceptible to corruption than serial flash since it is completed quickly. by contrast, serial flash requiring milliseconds to write is vulnerable to noise during much of the cycle. serial peripheral interface ? spi bus the fm25v10 employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 40mhz. this high-speed serial bus provides high performance serial communication to a host microcontroller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm25v10 operates in spi mode 0 and 3. protocol overview the spi interface is a synchronous serial interface using clock and data pins. it is intended to support multiple devices on the bus. each device is activated using a chip select. once chip select is activated by the bus master, the fm25v10 will begin monitoring the clock and data lines. the relationship between the falling edge of /s, the clock and data is dictated by the spi mode. the device will make a determination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm25v10 supports only modes 0 and 3. figure 2 shows the required signal relationships for modes 0 and 3. for both modes, data is clocked into the fm25v10 on the rising edge of c and data is expected on the first rising edge after /s goes active. if the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. the spi protocol is controlled by op-codes. these op-codes specify the commands to the device. after /s is activated the first byte transferred from the bus master is the op-code. following the op-code, any addresses and data are then transferred. certain op-codes are commands with no subsequent data transfer. the /s must go inactive after an operation is complete and before a new op-code can be issued. there is one valid op-code only per active chip select. spi mode 0: cpol=0, cpha=0 spi mode 3: cpol=1, cpha=1 figure 2. spi modes 0 & 3
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 4 of 16 system hookup the spi interface uses a total of four pins: clock, data-in, data-out, and chip select. a typical system configuration uses one or more fm25v10 devices with a microcontroller that has a dedicated spi port, as figure 3 illustrates. note that the clock, data-in, and data-out pins are common among all devices. the chip select and hold pins must be driven separately for each fm25v10 device. for a microcontroller that has no dedicated spi bus, a general purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins together and tie off the hold pin. figure 4 shows a configuration that uses only three pins. figure 3. 2mbit (256kb) system configuration with spi port figure 4. system configuration without spi port
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 5 of 16 power up to first access the fm25v10 is not accessible for a period of time (t pu ) after power up. users must comply with the timing parameter t pu , which is the minimum time from v dd (min) to the first /s low. data transfer all data transfers to and from the fm25v10 occur in 8-bit groups. they are synchronized to the clock signal (c), and they transfer most significant bit (msb) first. serial inputs are registered on the rising edge of c. outputs are driven from the falling edge of clock c. command structure there are ten commands called op-codes that can be issued by the bus master to the fm25v10. they are listed in the table below. these op-codes control the functions performed by the memory. they can be divided into three categories. first, there are commands that have no subsequent operations. they perform a single function, such as to enable a write operation. second are commands followed by one byte, either in or out. they operate on the status register. the third group includes commands for memory transactions followed by address and one or more bytes of data. table 1. op-code commands name description op-code wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b fstrd fast read memory data 0000 1011b write write memory data 0000 0010b sleep enter sleep mode 1011 1001b rdid read device id 1001 1111b snr read s/n 1100 0011b wren ? set write enable latch the fm25v10 will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op-code will allow the user to issue subsequent op-codes for write operations. these include writing the status register (wrsr) and writing the memory (write). sending the wren op-code causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit. completing any write operation will automatically clear the write-enable latch and prevent further writes without another wren command. figure 5 below illustrates the wren command bus configuration. 0 0 0 0 0 1 1 0 s c d q hi-z 0 1 2 3 4 5 6 7 figure 5. wren bus configuration wrdi ? write disable the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. 0 0 0 0 0 1 0 0 s c d q hi-z 0 1 2 3 4 5 6 7 figure 6. wrdi bus configuration rdsr ? read status register the rdsr command allows the bus master to verify the contents of the status register. reading status provides information about the current state of the write protection features. following the rdsr op-code, the fm25v10 will return one byte with the contents of the status register. the status register is described in detail in the section below.
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 6 of 16 wrsr ? write status register the wrsr command allows the user to select certain write protection features by writing a byte to the status register. prior to issuing a wrsr command, the /w pin must be high or inactive. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a write operation and therefore clears the write enable latch. the bus configuration of rdsr and wrsr are shown below. figure 7. rdsr bus configuration figure 8. wrsr bus configuration status register & write protection the write protection features of the fm25v10 are multi-tiered. taking the /w pin to a logic low state is the hardware write-protect function. status register write operations are blocked when /w is low. to write the memory with /w high, a wren op-code must first be issued. assuming that writes are enabled using wren and by /w, writes to memory are controlled by the status register. as described above, writes to the status register are performed using the wrsr command and subject to the /w pin. the status register is organized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name wpen 1 0 0 bp1 bp0 wel 0 bits 0, 4, 5 are fixed at 0 and bit 6 is fixed at 1, and none of these bits can be modified. note that bit 0 (?ready? in serial flash) is unnecessary as the f- ram writes in real-time and is never busy, so it reads out as a ?0?. there is an exception to this when the device is waking up from sleep mode, which is described on the following page. the bp1 and bp0 control software write protection features. they are nonvolatile (shaded yellow). the wel flag indicates the state of the write enable latch. attempting to directly write the wel bit in the status register has no effect on its state. this bit is internally set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify portions of memory that are write- protected as shown in the following table. table 3. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 18000h to 1ffffh (upper ?) 1 0 10000h to 1ffffh (upper ?) 1 1 00000h to 1ffffh (all) the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the wpen bit controls the effect of the hardware /w pin. when wpen is low, the /w pin is ignored. when wpen is high, the /w pin controls write access to the status register. thus the status register is write protected if wpen=1 and /w=0. this scheme provides a write protection mechanism, which can prevent software from writing the memory s c d q s c d q
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 7 of 16 under any circumstances. this occurs if the bp1 and bp0 bits are set to 1, the wpen bit is set to 1, and the /w pin is low. this occurs because the block protect bits prevent writing memory and the /w signal in hardware prevents altering the block protect bits (if wpen is high). therefore in this condition, hardware must be involved in allowing a write operation. the following table summarizes the write protection conditions. table 4. write protection wel wpen /w protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected memory operation the spi interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the f-ram technology. unlike serial flash, the fm25v10 can perform sequential writes at bus speed. no page buffer is needed and any number of sequential writes may be performed. write operation all writes to the memory array begin with a wren op-code. the next op-code is the write instruction. this op-code is followed by a three-byte address value, which specifies the 17-bit address of the first data byte of the write operation. subsequent bytes are data and they are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 1ffffh is reached, the counter will roll over to 00000h. data is written msb first. a write operation is shown in figure 9. unlike serial flash, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8 th clock). the rising edge of /s terminates a write op-code operation. asserting /w active in the middle of a write operation will have no effect until the next falling edge of /s. read operation after the falling edge of /s, the bus master can issue a read op-code. following this instruction is a three-byte address value (a16-a0), specifying the address of the first data byte of the read operation. after the op-code and address are complete, the d pin is ignored. the bus master issues 8 clocks, with one bit read out for each. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 1ffffh is reached, the counter will roll over to 00000h. data is read msb first. the rising edge of /s terminates a read op- code operation and tri-states the q pin. a read operation is shown in figure 10. fast read operation the fm25v10 supports the fast read op-code (0bh) that is found on serial flash devices. it is implemented for code compatibility with serial flash devices. following this instruction is a three-byte address (a16-a0), specifying the address of the first data byte of the read operation. a dummy byte follows the address. it inserts one byte of read latency. the d pin is ignored after the op-code, 3- byte address, and dummy byte are complete. the bus master issues 8 clocks, with one bit read out for each. the fast read operation is otherwise the same as an ordinary read. if the last address of 1ffffh is reached, the counter will roll over to 00000h. data is read msb first. the rising edge of /s terminates a fast read op-code operation and tri-states the q pin. a fast read operation is shown in figure 11. hold the fm25v10 and fm25vn10 devices have a /hold pin that can be used to interrupt a serial operation without aborting it. if the bus master pulls the /hold pin low while c is low, the current operation will pause. taking the /hold pin high while c is low will resume an operation. the transitions of /hold must occur while c is low, but the c and /s pins can toggle during a hold state.
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 8 of 16 figure 9. memory write with 3-byte address figure 10. memory read with 3-byte address figure 11. fast read with 3-byte address and dummy byte 7 6 0 1 2 34567 0 1 2 3 5 4567 0 1 2 34567 op-code 0 0 0 0 1 0 1 msb 17-bit address 0 0 0 0 a1 x x x x 76543210 lsb msb lsb dat a 1 a2 s c d q a0 dummy byte 7 6 0 1 2 34567 0 1 2 34 5 4567 0 1 2 34567 op-code 0 0 0 0 0 0 1 msb 17-bit a dd r ess 0 0 0 0 0 0 76543210 lsb msb lsb dat a 1 0 s c d q a 16 a3 a1 a2 a0 0 1 2 34567 0 1 2 345 op-c ode 0 0 0 0 0 0 1 0 m sb 17-bit add r es s 0 0 6 0 0 0 0 0 s c d q 7 a 16 a1 a2 a3 4567 0 1 2 34567 a0 76543210 lsb m sb lsb d ata
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 9 of 16 sleep mode a low power mode called sleep mode is implemented on both fm25v10 and fm25vn10 devices. the device will enter this low power state when the sleep op-code b9h is clocked-in and a rising edge of /s is applied. once in sleep mode, the c and d pins are ignored and q will be high-z, but the device continues to monitor the /s pin. on the next falling edge of /s, the device will return to normal operation within t rec (400 s max.). the q pin remains in a hi-z state during the wakeup period. the device will not necessarily respond to an opcode within the wakeup period. to start the wakeup procedure, the controller may send a ?dummy? read, for example, and wait the remaining t rec time. figure 12. sleep mode entry device id the fm25v10 and fm25vn10 devices can be interrogated for its manufacturer, product identification, and die revision. the rdid op-code 9fh allows the user to read the manufacturer id and product id, both of which are read-only bytes. the jedec-assigned manufacturer id places the ramtron identifier in bank 7, therefore there are six bytes of the continuation code 7fh followed by the single byte c2h. there are two bytes of product id, which includes a family code, a density code, a sub code, and product revision code. table 6. manufacturer and product id bit 7 6 5 4 3 2 1 0 hex manufacturer id 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 1 1 0 0 0 0 1 0 c2 jedec assigned ramtron c2h in bank 7 family density hex device id (1 st byte) 0 0 1 0 0 1 0 0 24h density: 01h=128k, 02h=256k, 03h=512k, 04=1m sub rev. rsvd device id (2 n d byte) 0 0 0 0 0 0 0 0 00h 00h=fm25v10, 01h=fm25vn10 figure 13. read device id s c d q enter sleep mode s c d q 7fh ? 7fh c2 h 00 h six bytes of continuation code 7fh 9fh 24 h 1 6 . . . . . . .
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 10 of 16 unique serial number (fm25vn10 only) the fm25vn10 device incorporates a read-only 8- byte serial number. it can be used to uniquely identify a pc board or system. the serial number includes a 40-bit unique number, an 8-bit crc, and a 16-bit number that can be defined upon request by the customer. if a customer-specific number is not requested, the 16-bit customer identifier is 0x0000. the serial number is read by issuing the snr op- code (c3h). the 8-bit crc value can be used to compare to the value calculated by the controller. if the two values match, then the communication between slave and master was performed without errors. the function (shown below) is used to calculate the crc value. to perform the calculation, 7 bytes of data are filled into a memory buffer in the same order as they are read from the part ? i.e. byte7, byte6, byte5, byte4, byte3, byte2, byte1 of the serial number. the calculation is performed on the 7 bytes, and the result should match the final byte out from the part which is byte0, the 8-bit crc value. customer identifier * 40-bit unique number 8-bit crc sn(63:56) sn(55:48) sn(47:40) sn(39:32) sn(31:24) sn(23:16) sn(15:8) sn(7:0) * contact factory for requesting a customer identifier number. figure 14. 8-byte serial number (read-only) function to calculate crc byte calccrc8( byte* pdata, int nbytes ) { static byte crctable[256] = { 0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d, 0x70, 0x77, 0x7e, 0x79, 0x6c, 0x6b, 0x62, 0x65, 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d, 0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb, 0xf2, 0xf5, 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd, 0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85, 0xa8, 0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd, 0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2, 0xff, 0xf8, 0xf1, 0xf6, 0xe3, 0xe4, 0xed, 0xea, 0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2, 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d, 0x9a, 0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32, 0x1f, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0d, 0x0a, 0x57, 0x50, 0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42, 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a, 0x89, 0x8e, 0x87, 0x80, 0x95, 0x92, 0x9b, 0x9c, 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4, 0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec, 0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4, 0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c, 0x51, 0x56, 0x5f, 0x58, 0x4d, 0x4a, 0x43, 0x44, 0x19, 0x1e, 0x17, 0x10, 0x05, 0x02, 0x0b, 0x0c, 0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a, 0x33, 0x34, 0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b, 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63, 0x3e, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b, 0x06, 0x01, 0x08, 0x0f, 0x1a, 0x1d, 0x14, 0x13, 0xae, 0xa9, 0xa0, 0xa7, 0xb2, 0xb5, 0xbc, 0xbb, 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83, 0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc, 0xcb, 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3 }; byte crc = 0; while( nbytes-- ) crc = crctable[crc ^ *pdata++]; return crc; }
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 11 of 16 figure 15. read serial number endurance the fm25v10 and fm25vn10 devices are capable of being accessed at least 10 14 times, reads or writes. an f-ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f-ram architecture is based on an array of rows and columns. rows are defined by a16-a3 and column addresses by a2-a0. see block diagram (pg 2) which shows the array as 16k rows of 64-bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation. the table below shows endurance calculations for 64-byte repeating loop, which includes an op-code, a starting address, and a sequential 64-byte data stream. this causes each byte to experience one endurance cycle through the loop. f-ram read and write endurance is virtually unlimited even at 40mhz clock rate. table 7. time to reach 100 trillion cycles for repeating 64-byte loop sck freq (mhz) endurance cycles/sec. endurance cycles/year years to reach 10 14 cycles 40 73,520 2.32 x 10 12 43.2 20 36,760 1.16 x 10 12 86.4 10 18,380 5.79 x 10 11 172.7 5 9,190 2.90 x 10 11 345.4 s c d q byte 7 byte 6 . . . c3 h . . . . . . . byte 1 byte 0
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 12 of 16 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +4.5v v in voltage on any pin with respect to v ss -1.0v to +4.5v and v in < v dd +1.0v t stg storage temperature -55 c to + 125 c t lead lead temperature (soldering, 10 seconds) 260 c v esd electrostatic discharge voltage - human body model (aec-q100-002 rev. e) - charged device model (aec-q100-011 rev. b) - machine model (aec-q100-003 rev. e) 4kv 1.25kv 200v package moisture sensitivity level msl-1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. dc operating conditions (t a = -40 c to + 85 c, v dd = 2.0v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage 2.0 3.3 3.6 v i dd power supply operating current @ c = 1 mhz @ c = 40 mhz - 1.5 0.3 3.0 ma ma 1 i sb standby current 90 150 a 2 i zz sleep mode current 5 8 a 3 i li input leakage current - 1 a 4 i lo output leakage current - 1 a 4 v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage -0.3 0.3 v dd v v oh1 output high voltage ( i oh = -1 ma, v dd =2.7v) 2.4 - v v oh2 output high voltage ( i oh = -100 a) v dd -0.2 - v v ol1 output low voltage ( i ol = 2 ma, v dd =2.7v) - 0.4 v v ol2 output low voltage ( i ol = 150 a) - 0.2 v r in input resistance (/hold pin) for v in = v ih (min) for v in = v il (max) 40 1 k ? m ? 5 notes 1. c toggling between v dd -0.2v and v ss , other inputs v ss or v dd -0.2v. 2. /s=v dd . all inputs v ss or v dd . 3. in sleep mode and /s=v dd . all inputs v ss or v dd . 4. v ss v in v dd and v ss v out v dd . 5. the input pull-up circuit is stronger (> 40k ? ) when the input voltage is above v ih and weak (> 1m ? ) when the input voltage is below v il . data retention (t a = -40 c to + 85 c) parameter min max units notes data retention 10 - years
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 13 of 16 ac parameters (t a = -40 c to + 85 c, c l = 30pf, unless otherwise specified) v dd 2.0 to 2.7v v dd 2.7 to 3.6v symbol parameter min max min max units notes f c c clock frequency 0 25 0 40 mhz t ch clock high time 20 11 ns 1 t cl clock low time 20 11 ns 1 t csu chip select setup 12 10 ns t csh chip select hold 12 10 ns t od output disable time 20 12 ns 2 t odv output data valid time 18 9 ns t oh output hold time 0 0 ns t d deselect time 60 40 ns t r data in rise time 50 50 ns 2,3 t f data in fall time 50 50 ns 2,3 t su data setup time 8 5 ns t h data hold time 8 5 ns t hs /hold setup time 12 10 ns t hh /hold hold time 12 10 ns t hz /hold low to hi-z 25 20 ns 2 t lz /hold high to data active 25 20 ns 2 notes 1. t ch + t cl = 1/f c . 2. this parameter is characterized but not 100% tested. 3. rise and fall times measured between 10% and 90% of waveform. capacitance (t a = 25 c, f=1.0 mhz, v dd = 3.3v) symbol parameter min max units notes c o output capacitance (q) - 8 pf 1 c i input capacitance - 6 pf 1 notes 1. this parameter is characterized and not 100% tested. ac test conditions input pulse levels 10% and 90% of v dd input rise and fall times 3 ns input and output timing levels 0.5 v dd output load capacitance 30 pf serial data bus timing
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 14 of 16 /hold timing s c q hold t hs t hh t hz t lz t hs t hh power cycle timing v dd min. v dd s t vr t pd t pu t vf power cycle & sleep timing (t a = -40 c to + 85 c, v dd = 2.0v to 3.6v, unless otherwise specified) symbol parameter min max units notes t vr v dd rise time 50 - s/v 1,2 t vf v dd fall time 100 - s/v 1,2 t pu power up (v dd min) to first access (/s low) 250 - s t pd last access (/s high) to power down (v dd min) 0 - s t rec recovery time from sleep mode - 400 s notes 1. this parameter is characterized and not 100% tested. 2. slope measured at any point on v dd waveform.
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 15 of 16 mechanical drawing 8-pin soic (jedec ms-012 variation aa) pin 1 3.90 0.10 6.00 0.20 4.90 0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45 0.40 1.27 0.19 0.25 0 - 8 recommended pcb footprint 7.70 0.65 1.27 2.00 3.70 refer to jedec ms-012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xxxxx= part number, p=package type r=rev code, lllllll= lot code ric=ramtron int?l corp, yy=year, ww=work week example: fm25v10, ?green?/rohs soic package, rev. a, lot 9646447, year 2010, work week 11 without s/n feature with s/n feature fm25v10-g fm25vn10-g a9646447 a9646447 ric1011 ric1011 xxxxxx-p rlllllll ricyyww
fm25v10 - 1mb spi fram rev. 2.0 may 2010 page 16 of 16 revision history revision date summary 1.0 8/29/2008 initial release. 1.1 10/6/2009 updated esd ratings. added tape and reel ordering information. updated lead temperature rating in abs max table. expanded crc check description. 2.0 5/25/2010 changed to pre-production status. changed part marking scheme. ordering information part number features operating voltage package fm25v10-g device id 2.0-3.6v 8-pin ?green?/rohs soic fm25vn10-g device id, s/n 2.0-3.6v 8-pin ?green?/rohs soic FM25V10-GTR device id 2.0-3.6v 8-pin ?green?/rohs soic in tape & reel fm25vn10-gtr device id, s/n 2.0-3.6v 8-pin ?green?/rohs soic in tape & reel

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